LSP speech synthesis ASIC architecture

A speech synthesis ASIC based on the line spectrum pair (LSP) scheme has been designed. In this ASIC, we encoded the LSP parameters with 4-bit Differential Quantization, and designed a two's complement 12-bit fixed-point serial pipeline arithmetic operations with rounding to perform the operations of the LSP speech synthesis digital filter. Finally, we verified our design for Chinese single-syllable pronunciations and continuous speech using FPGA, and obtained good synthetic speech at low bit rate (about 2.2 kbps).