A circuit design for 2-Gbit/s Si bipolar crosspoint switch LSIs

An 8*8 and an expandable 16*16 crosspoint switch LSI utilizing a new circuit design and super self-aligned process technology (SST-1A) are discussed. The LSIs successfully switched with a bit error rate of less than 10/sup -9/ at 2.5 Gb/s using a 2/sup 9/-1 pseudorandom NRZ sequence. Pulse jitter was limited to less than 80 ps at 1.2 Gb/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell, including a selector. The LSIs have an ECL-compatible interface, -4-V and -2-V power supply voltages, and a power dissipation of less than 0.9 W for the 8*8 LSI and 2.8 W for the expandable 16*16 LSI.<
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