CMOS subnanosecond true-ECL output buffer

An emitter coupled logic (ECL) 100 K compatible output buffer circuit fabricated in a submicrometer CMOS-only process is presented. High speed (0.9-ns delay) and sufficient precision are achieved through the use of a novel circuit principle. Negative feedback and an error correction technique are applied in such a way that external components and/or additional power supplies are not required. Aspects of stability and accuracy are investigated and simulation results are discussed to explain the circuit technique. The actual design and practical aspects of it, such as layout, implementation in silicon, and technology features, are shown. Measured and simulation results, showing the good performance of the ECL output buffer across a wide range of capacitive loading, are presented.<
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