A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design

In a VLSI memory, noise generated by its own operation is a serious problem. The noise disturbs data sensing, especially in EPROMs which have a single-ended sensing scheme. To develop high-density and high-speed EPROMs, it is necessary to solve the noise problems. Incorrect EPROM functions due to the noise are discussed. High-noise-immunity circuit techniques for stable data sensing and high-speed access time are proposed. These are divided bit-line layout, reference line with dummy bit lines, and a chip-enable transition detector. Using these circuit techniques and 0.8- mu m n-well CMOS technology, a 512 K*8-b CMOS EPROM was developed. A 68-ns access time was achieved. The die size is 5.62 mm*15.30 mm, and it is assembled in a 600-mil cerdip package.<
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