A 3.8-ns 16 K BiCMOS SRAM

A 2 K*8-b, ECL 100 K compatible BiCMOS SRAM with 3.8-ns (-4.5 V, 60 degrees ) address access time is described. The precisely controlled bit-line voltage swing (60 mV), a current sensing method, and optimized ECL decoding circuits permit a reliable and fast readout operation. The SRAM features an on-chip write pulse generator, latches for input and output bits, and a full six-transistor CMOS cell array. Power dissipation is approximately 2 W, and the chip size is 3.9*5.9 mm/sup 2/. The SRAM was based on 1.2- mu m BiCMOS, using double-metal, triple-polysilicon, and self-aligned bipolar transistors.<
>