A self-aligned counter-doped well process utilizing channeling ion implantation

This paper describes a new self-aligned counter-doped well process realizing low junction capacitance CMOS's. This technology intentionally utilizes channeling ion implantation to achieve counter doping of the well in the same mask step as SD implantation. The benefit of this technology is its process simplicity with full compatibility with the conventional CMOS process. Applying this technology to a 0.25-/spl mu/m CMOS process, a 50%-70% reduction in junction capacitance is achieved, and an 18.3% improvement in simulated propagation delay time is demonstrated for 0.25-/spl mu/m CMOS inverter chains under 0.9-V operation.