A scalable chip set for MPEG2 real-time encoding

This is a description of an architecture for video compression based on the MPEG2 (MP@ML) standard. The chip set is comprised of 3 different devices. The architecture is scalable, and real-time MPEG2 systems could be built with one, two or all three chip solutions. The encoder includes an on-chip processor for programming options, and provides direct connections to external DRAM and SRAM.