Design Verification and Testing of the WE 32100 CPUs

This article reviews the design verification and testing methods that evolved during the development of four AT&T 32-bit microprocessors. Software modeling and regression testing-without hardware breadboards-proved to be a viable approach for these high-performance CPU chips. AT&T investigated five built-in testability features: a compressed-data output pin, macro-ROM internal access, register/PLA internal access, self-test macro-ROM code, and a board-level tri-state feature. Internal probing in a bench-top facility was more efficient than software-based, internal access-oriented debugging, and fault simulations were performed to confirm the design, layout, and physical tests.