A novel 0.25 /spl mu/m CMOS technology for 6.82 /spl mu/m/sup 2/ 6-Tr. SRAM cell with elevated trench isolation and line-and-space shaped gates (ETILS)

Miniaturization of SRAM cell size is a key issue for multi-media logic CMOS LSIs, such as DSP and MPEG2 decoders/encoders. Recently, several CMOS technologies realizing small cell size less than 10 /spl mu/m/sup 2/ have been reported, while the previous work by M. Minami et al. (1995) achieved an even smaller cell size of 6.93 /spl mu/m/sup 2/, but this process required two-level local-interconnect. In this paper, a novel 0.25 /spl mu/m CMOS technology is developed by an elevated trench isolation technology and line-and-space shaped gate formation (ETILS). This process allows the smallest cell size of 6.82 /spl mu/m/sup 2/ with simple single-level local-interconnect.