Giga-bit DRAM cells with low capacitance and low resistance bit-lines on buried MOSFETs and capacitors by using bonded SOI technology-reversed stacked capacitor (RSTC) cell

This paper describes a reversed-stacked-capacitor (RSTC) cell for Giga-bit DRAMs, where a storage capacitor and a MOSFET are reversed by using chemical-mechanical-polishing (CMP) and bonded-SOI technology. The virtual flat surface at the bottom of the MOSFET is made into a real surface by polishing. The bit-lines and metal wirings are realized on the flat surface with low-aspect-ratio contact holes throughout the whole chip. This cell structure is suitable for not only Giga-bit DRAMs but also embedded DRAMs. A test memory array is fabricated with a 64 Mbit DRAM design rule. Both capacitance and resistance of bit-lines decreased by a factor of two with this RSTC cell compared to the conventional shielded-bit-line STC cells. The bit-lines are placed far from word-lines and cell-capacitors. The bit-lines are made of low resistivity materials after all the high-temperature processes have been finished.