A 0.25 /spl mu/m CMOS technology with 45 /spl Aring/ NO-nitrided oxide

This paper describes the device design and fabrication of a 0.25 /spl mu/m CMOS process integrated with 45 /spl Aring/ oxynitride gate dielectric for high-performance logic applications. Channel profile engineering is applied to control short-channel effects. With TiN-capped Co salicide, the gate sheet resistance is reduced to less than 5 /spl Omega//sq at 0.18 /spl mu/m. Ring oscillator gate delay of 26 ps/stage is accomplished at a supply voltage of 1.8 V.