0.228 /spl mu/m/sup 2/ trench cell technologies with bottle-shaped capacitor for 1 Gbit DRAMs

In order to realize 1 Gbit DRAMs, we have developed a 0.228 /spl mu/m/sup 2/ trench type cell. Two methods are employed to shrink the memory cell size. One is a "bottle shaped" capacitor, which has a larger diameter than the opening for the storage node. For this capacitor structure, we have verified 30% capacitance increase keeping the trench opening, sufficiently high breakdown field of capacitor dielectric, and less than 1/1000 of a soft-error rate compared with the conventional one. The other is a 6F/sup 2/ cell layout suitable for an open-folded-bit-line architecture, which reduces to 75% for the conventional 8F/sup 2/ cell layout with the same feature size, F. We have also confirmed that a P/sup +/ poly gate transistor has a sufficient overlap tolerance (more than 0.1 /spl mu/m) between the transfer gate and the trench edge by using three-dimensional device simulator. These results strongly support feasibility of our novel cell.