Novel contamination restrained silicidation processing using load-lock LPCVD-films and lightly doped deep drain (LD/sup 3/) structure for deep submicron dual gate CMOS

A novel low leakage, low resistance and high temperature stability titanium salicide process named "Silicidation after ion Implantation through the Contamination-Restrained Oxygen free LPCVD-Nitride layer in a Lightly Doped diffusion layer (LD-SICRON)" has been developed. This novel LD-SICRON process has been successfully implemented in deep submicron dual gate CMOS development. Junction leakage current for TiSi/sub 2/-n/sup +//p and -p/sup +//n was reduced to the non-silicidation level (area component: 0.8/spl sim/3.6 nA/cm/sup 2/, peripheral component: 3.1/spl sim/3.6 pA/cm). Low sheet resistances of n/sup +/- and p/sup +/-gate electrodes (4 /spl Omega//square) were maintained below the 0.2 /spl mu/m line even after high temperature annealing (1000/spl deg/C, 10 sec+850/spl deg/C, 30 min.).