A scaling scheme for interconnect in deep-submicron processes

In this paper, we study the requirements for interconnect in deep-submicron technologies and identify critical factors that will require innovations in process technology, process integration and circuit-and-system design techniques. We also propose a scaling scheme for global lines to optimize the interconnect for a given application domain such as microprocessors, ASICs or memory. For local interconnect we demonstrate that cross-talk is the major challenge which can be addressed by selectively using larger drivers to reduce cross-talk noise when necessary.