Intra-die device parameter variations and their impact on digital CMOS gates at low supply voltages

Statistical intra-die variations of device parameters from a 0.5 /spl mu/m CMOS process are determined, finding good agreement with the (WL)/sup -1/2/ model. It is proven that channel doping variations are responsible. Additionally, systematic proximity-induced parameter deviations due to different field oxide surroundings are found. The resulting variations of inverter delays for different supply voltages and gate areas are determined.