ASIC implementation of a RISC microprocessor for portable workstation

This paper describes the HDL based design of a RISC microprocessor for portable workstation which especially requires both cost effectiveness and highly integrated functions. Based on 0.6 /spl mu/m TLM CMOS technology, this chip includes IU, MMU/CC, bus controller, and address translation memory in a 1.1 cm/sup 2/ die size, and operates at 45 MHz. Both fast design time and the easiness of full functional verification could be feasible with standard cell based design methodology and pseudo system modelling.