VLSI realization of a 16/spl times/16 ATM switch using 1 /spl mu/m CMOS technology

This paper describes the realization of a chipset of two VLSIs for a 16/spl times/16 ATM switch using 1 /spl mu/m CMOS technology. The chipset can run up to 500 Mbps per port. The design is based on the pipeline Banyan architecture, which has the features of sequential packet delivery, low hardware complexity, and a close to 100% maximum throughput.