Micro yield modeling for IC processes

A methodology to model IC yield variations among products and processes has been developed. This methodology decomposes the product yield into a non-random systematic yield term Y/sub s/ and a random yield term Y/sub r/, and models them independently. The systematic yield portion of the product yield is extracted by multiple die yield analysis, while the random portion of the product yield is modeled using test chip data and product layout analysis of yield sensitive areas. Furthermore, the micro yield model is capable of not only making real time product yield projections, but is also capable of providing confidence intervals around those projections. Experimental results show good agreement between the predicted and actual product yields.