A new CMOS analog multiplier with improved input linearity

A new CMOS four-quadrant analog multiplier is presented. By means of an unique nonlinear compensation technique, the linear input range of the multiplier is extended significantly. The simulation results show that, when V/sub y/=/spl plusmn/3V, the nonlinear error is less than 0.94% over the /spl plusmn/3V input range of V/sub x/ and when V/sub x/=/spl plusmn/3V, the nonlinear error is less than 0.25% over the /spl plusmn/3V input range of V/sub y/, with a power supply of /spl plusmn/5V.