A Mixed-Signal BIST Scheme for ADCs in SoC and its FPGA Implementation

A novel Mixed-Signal BIST scheme that is capable of calculating dynamic and static parameters of ADCs is proposed. By elaborately integrating test capability of both dynamic and static test uniformly in one BIST circuit, as well as reusing and organizing the elemental operative units and memories for analog stimulus generation and response analysis, hardware overhead is restricted to the minimum with very little impact on test quality. The proposed scheme is implemented and verified in FPGA thereby validates the viability and flexibility of the design.