Noise computation in single chip packages

This paper describes the computation of noise in single chip packages forming an integral part of a larger system. An analysis tool is discussed that integrates the details of chip, first level, and second level packages to form a network for simulation. The tool is useful in the computation of noise generated by single chip packages and allows for post-layout, pre-fabrication noise estimation. This paper provides details on the components of noise including resonance which is often over looked in most computations. Time domain measurements have been used to validate the noise analysis.