Long chain digital MOS transistor optimal design

This paper presents a method for optimal transistor sizing in digital circuits that contain long chains of transistors. First a new analytical model for the delay time is presented. Second, this model is compared to other models previously available, including the standard RC mesh model. Using the new model, delay time estimation fits well on SPICE simulations even for a small number of transistors and with load in an extended range. This model is included in an delay optimization tool that leads to delay improvement of up to 20% for constant cell area.