An approach for a dynamic generation/validation system for the functional simulation considering timing constraints

This paper presents a method for the automatic validation of the timing behavior of RT and gate level VHDL descriptions. Using a machine-readable timing specification, we automatically create a VHDL testbench for the stimuli generation and the validation of the expected responses. We have developed a VHDL package using linear programming algorithms to compute a valid set of stimuli. The model responses are checked dynamically subject to the model outputs. A graphical interface is used to specify and validate a timing diagram.