Addressing the Challenges of System-On-A-Chip Design

Summary form only given, as follows. While systems-on-silicon (SOS) products can range from cellular phones to 200-pound avionics communications and navigation systems, they present common problems to the EDA and semiconductor industries. First, SOS applications demand very high levels of integration and functionality, which can only be met through new sub-micron IC technologies. Second, they embrace both the digital and analog domains with equal complexity, and demand tools that integrate these domains into a single silicon chip. Third, to deliver the required bandwidths, SOS applications must run at very high clock speeds and often operate in the RF realm, with all its attendant design challenges. The author will show how current EDA methodologies and tool technologies will evolve to fit the system on silicon paradigm. In the course of this evolution, the EDA resources used to implement rapid time-to-market designs-top-down synthesis into FPGA or ASIC formats-will migrate into the realm of more complex, full-custom designs that embrace entire electronic systems. This migratory pattern will not be without its challenges. Top-down design flows for FPGAs and ASICs have matured into highly integrated processes that reconcile the creation, synthesis, and physical layout phases of the design cycle. As these same EDA tools migrate into the custom IC arena of systems on silicon, they must retain the integrity of their processes and flows-even though they are now dealing with unprecedented levels of complexity, and integrating software development tools. Further, they must provide an effective means of preserving and exploiting intellectual property for design re-use. In addition, the author will address such issues as the role of power management, integrated design flow, and deep submicron physical effects that are associated with successfully overcoming the challenges of system-on-silicon design.