Algorithm based fault tolerant synthesis for linear operations

High-level synthesis is becoming more important in practical design environments to meet new system requirements and, increasingly, fault tolerance is one especially because of high-speed and low power demands. This paper explores several basic aspects of low-cost fault tolerant synthesis for practical linear systems. It deals with practical design constraints that require basic operations to be only performed by a limited processing resources and do not normally assign each operation a separate processing resource. Two core issues, partitioning and allocation, for fault tolerant synthesis are examined. Results demonstrate a high-level abstraction and framework for fault tolerant synthesis which is almost totally independent of the physical hardware implementation. Issues in designing 1-fault detectable FFT system are considered in detail to illustrate the significance and effects of fault tolerant synthesis schemes. Our ultimate goal is to incorporate these techniques in future automated design tools so that fault tolerance features can be part of the design options.