Higher order logic in reasoning about asynchronous circuits

A formal process description of a delay insensitive asynchronous circuit (DIAC) in real time CSP mechanized in the higher order logic proof system (RTCSP-HOL) is presented. The syntax, process definitions, ontimeness, and deductions over time in RTCS-HOL are given. The delay caused by a wire in a DIAC is modeled using the wait process in RTCSP-HOL. The delay insensitivity of two gates in a C element is proved in terms of the timeliness of the processing of input signals by the two gates. The paper presents an illustration of how a DIAC designer might mechanize the formal specification and analysis of the behavior of DIACs and prove the delay insensitivity of a particular configuration of a DIAC.