Guided synthesis and formal verification techniques for parameterized hardware modules

A method is proposed for either guided synthesis or formal correctness verification of parameterized digital hardware modules. It starts from a high-level parameterized description of the module, which is used as the specification. The method is based on the concept of correctness-preserving transformations. These transformations are described in a formal way by means of transformation descriptions. It ends at a lower-level parameterized structure description of the implementation. Direct manipulations are done using an existing hardware description language that emphasizes a strict separation between parameterized structure description and behavior description. The concepts have been applied to real VLSI design vehicles such as a pipelined and parameterized multiplier accumulator module and systolic implementation of an FIR filter. The methods presented here are easily adaptable to use in CAD.<
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