Mitigating and tolerating SEU effects in switch modules of SRAM-based FPGAs

This paper proposes three methods to mitigate and tolerate SEU-caused errors on the configuration bits of SRAM-based field programmable gate arrays. The proposed methods are based on error detection and correction codes which are able to detect or correct SEU-caused errors in Switch Modules. The effects of proposed methods on the various parameters such as area, delay and power consumption for ten ITC'99 benchmark circuits have been evaluated with synopsis
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CAD tool and compared with previous work. The experimental results show that the proposed methods can detect or correct 100% single errors in Switch Modules by imposing area overhead between 2% and 60%, delay overhead between 25% and 100% and power consumption overhead between 1% and 25%.