Thermal stress analysis of a multichip package design

The authors present a thermal analysis of a thin-film multichip package design, with emphasis on thermally induced stress in the critical package components. The package uses flip-chip solder bonding and thin-film interconnections between chips. Indium was chosen as the die attachment medium between each chip and the water-cooled heat sink. A methodology is given to estimate the stresses in the structure during a power-up. Finite-difference and finite-element computer simulations were used to calculate the temperature and stress distributions under both transient and steady-state conditions. It is shown how thermal gradients, expansion mismatches, and global bending of the structure determine the stress distribution. The components in the module have various thermal time constants, and the stresses during a transient are related to the rate at which each component heats up. For instance, the chips and the heat sink complete 70% of their temperature rise in the first 200 ms, but the substrate takes over 10 s to reach 70% of its steady-state temperature rise. Therefore, even if a design is optimized to be thermal expansion matched under operating conditions, stresses can develop during a transient.<
>