Parallel concurrent path-delay fault simulation using single-input change patterns

We present a new simulation-based method using single-input change (SIC) patterns to efficiently derive tests for singly-testable (ST) path-delay faults (PDFs). We assign random values to all inputs, and then propagate rising and falling transitions from each input while all other inputs are held steady. We present a sixteen-valued algebra with which rising and falling PDFs from all inputs are concurrently simulated. Using a suitable encoding for signal values, gates are evaluated directly through Boolean operations, and all computation stages use machine word parallelism. Results on, the ISCAS '85 and '89 benchmarks show that the method runs seven times faster than another published method (with normalized CPU times), and detects 76% more ST PDFs.