Low power realization of FIR filters using multirate architectures

The paper presents low power realization of FIR filters using multirate architectures. The multirate architectures enable computationally efficient implementations of FIR filters. The computational complexity of these architectures is analysed and power analysis is presented to show how the computational efficiency can be exploited to reduce power dissipation. The results show upto 73% power reduction for dedicated ASIC implementation with no datapath area overhead. The paper also presents the implementation of the multirate architecture on the TMS320C2x/C5x programmable DSPs and shows that it can result in upto 43% power reduction.