Low-power, low-voltage BiCMOS comparators for /spl sim/200 MHz, 8 bit operation

Two novel BiCMOS latched comparators operating at 3.3 V with 8 bit resolution are presented. They achieve /spl sim/200 MHz operation and exhibit lower power consumption than the conventional architecture. The first resembles a conventional bipolar latched comparator, with a variable load resistance which changes its value three times during the acquisition cycle. It achieves the highest speed and the lowest power consumption. The second includes a differential amplifier which unbalances a ground-referenced latch by current mirror action. It may be adapted to even lower supply voltages and exhibits negligible kick-back effects.