A robust single phase clocking for low power, high-speed VLSI applications

Power dissipation is becoming a prime design constraint in VLSI systems. The new key words for evaluating a design's performance are low power and high speed. This requires an overall system design review that considers suitable algorithms, architectures, circuits, and technology. In synchronous systems, the clocking network sets the frame that contains the whole design. It must be simple and robust. Power consumption in the clock distribution network has usually been a substantial part of the system total power consumption. New true single phase latches and flip flops are presented that are slope-insensitive, fast, and have data dependent power consumption. Flip flops are presented that work between DC and 1.7 GHz clock frequencies in a 1 /spl mu/m CMOS technology. Methods are given that result in power saving in the clock system by reducing the clock rate by half for the same data throughput on the system level.