Novel ESD protection transistor including SiGe buried layer to reduce local temperature overheating

This paper introduces a new NMOS electrostatic discharge (ESD) protection transistor which contains a buried SiGe narrow-bandgap layer between the source and the drain region. The simulations carried out by a two-dimensional simulator show that the ESD induced current flows mainly through the buried layer in the new structure, which strongly suppresses local overheating on the silicon surface. As a result, the peak lattice temperature for the Machine Model with 300 V level is 400/spl deg/C in the new structure, which is much lower than in the normal structure, 1150/spl deg/C. In the new structure, the parasitic bipolar turn-on is faster and the bipolar current gain (/spl beta/) is higher than in the normal structure by as much as 8 ns and 10 times, respectively. The snapback voltage is reduced by 1.5 V in the new structure.