An effective BIST scheme for carry-save and carry-propagate array multipliers

Array multipliers, due to their high regularity, are efficiently designed as parts of complex VLSI devices. Such embedded multipliers have low controllability and observability, making the use of appropriate BIST schemes a necessity. This paper introduces a very effective BIST scheme for carry-propagate and carry-save array multipliers. The deterministic BIST patterns produced by the Test Pattern Generator provide a fault coverage larger than 99%. The required Test Pattern Generator consists of a simple binary counter or maximum length LFSR of a fixed size (8-bits), independent of the size of the multiplier. For Output Data Evaluation a count-based scheme is adopted. The novel BIST scheme does not require any DFT in the multiplier design and is generic, i.e. independent of specific implementations of the multiplier cells.