Testable design of non-scan sequential circuits using extra logic

Design of irredundant and fully testable non-scan synchronous sequential circuits is a major concern of logic synthesis. The presence of sequentially redundant faults (SRFs) makes test generation complicated, and hence their removal is highly desirable to enhance testability. In this paper, we propose a novel technique for testable design which is significantly different from scan designs, or testability-targeted synthesis approaches. We show that addition of some extra logic and a control input to an arbitrary sequential circuit can eliminate all equivalent and isomorph SRFs, even under the multiple stuck-at-fault model. Every pair of states can easily be distinguished in the modified machine, thus making it easily testable. The augmented logic is also universal, i.e., independent of the state diagram or the circuit structure of the given machine. Analysis of benchmark circuits reveals that its hardware overhead is much less compared to that of full scan design.