Modeling Approaches for Functional Verification of RF-SoCs: Limits and Future Requirements

Since the design and realization of a complex system on a chip is error prone, functional verification should have been a main task in today's design flows but is still underestimated. This paper gives an overview of current modeling approaches to handle functional verification of a design on the top level, prior to tape out. The problems that arise from the different approaches such as baseband modeling and event-driven modeling are explained, and the resulting effects on the simulated system specifications are presented. The necessity of the approaches for future systems, which are not simulatable with current methods, is presented, and the needed extensions of the hardware description languages and simulators are proposed.