Automatic generation of optimized DSP assembly code

This paper describes a data flow graph compiler for the analog devices fixed-point DSP family ADSP-210x. In the first step, the graphs are transformed into constrained expression trees. Next, optimized straight-line code is generated based on the trellis tree concept. Scheduling, register allocation, and instruction selection amount to looking for minimal weighted paths in trellis trees. In the final compaction step, instruction level parallelism is exploited by combining two or more instructions into one. Experimental results show that highly optimized instruction code can be produced within a very short compilation time.