3D Simulation Study of Cell-Cell Interference in Advanced NAND Flash Memory

A new Technology CAD (TCAD) methodology has been applied to accurately extract cell-cell interference. The new method uses a "DeltaVt ratio" model instead of the conventional "capacitance ratio" model. The new method will be introduced and validated by recent experimental data. The predictions of the cell-cell interference on sub-40 nm floating gate (FG) cells and charge trapped flash (CTF) cells will be discussed. Finally, the implications and challenges of Multilevel Cell (MLC) applications will be made.