Design of a flash A/D converter with dual-bootstrapped THA circuit

This paper describes a 6 bit 1 GS/s CMOS flash A/D converter using dual-bootstrapped THA circuit. The proposed flash architecture employs bootstrap technique in the track and hold circuit for low bit error ratio and high linearity. The measurement result shows a conversion rate of 1Gs/s, SNDR of 35.1dB, DNL/INL of plusmn0.65LSB/plusmn0.80LSB, and power dissipation of 228 mW at 1.8 V. The chip is implemented in a 0.18 mum CMOS 1-poly 6-metal technology and occupies an active area of 0.7 mm
²
.