A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs

A 0.6 V 45 nm dual-rail SRAM design utilizing an adaptive voltage regulator targeted for the SRAM compiler application is proposed for the first time. The proposed work describes an adaptive mechanism to generate Cell-Vdd (CVDD), which tracks a certain voltage offset with respect to the Logic-Vdd (VDD). This dual-rail solution provides a mean to lower the VDD down to 0.6 V. In this work, the bit-line (BL) is precharged to VDD instead of CVDD. The benefits of such design choice include the relaxation of the IR-drop constraints on the CVDD power mesh routing for P&R flow, and the quick recovery time for the BL to exit the leakage saving mode and precharge to full rail. This implementation can also reduce the congestion of the VDD and CVDD power mesh. A 45 nm test chip demonstrates that these concepts successfully push the minimum operational logic-Vdd voltage level (VDD_min) down to 0.6 V, which is more than 250$~$mV lower than the conventional single-rail SRAMs.