Design and implementation of MIC@R router for on-chip networks

The paper presents a design and implementation of router architecture suitable for Networks-on-Chip (NoC) design. This architecture offers lowest routing latency (1 cycle) and allows supporting several adaptive routing algorithms. Latency reduction is obtained by using Fast Parallel Routing (FPR) arbitration that consists in parallel processing and in one stage the routing decisions and arbitration. The proposed router architecture is implemented in ASIC technology and evaluated in 2D Mesh networks with three adaptive routing algorithms: Fully Adaptive (FA), Proximity Congestion Awareness (PCA) and Contention Look-Ahead (CLA). The obtained results show that our router, combined with adaptive routing techniques is effective in terms of latency and throughput.