Performance Analysis of Germanium Nanowire Tunneling Field Effect Transistors

Tunneling field effect transistors (FET), consisting of gate tunable p-i-n (p-type-intrinsic-n-type) device structures, represent an attractive and realistic paradigm that can potentially provide relief to the increasing power dissipation in high performance electronic applications. Such devices possess a subthreshold slope (SS) smaller than the thermally limited 60 mV/decade, but also can suffer from ambipolar device characteristics and an ON-state current significantly smaller than that of conventional metal-oxide-semiconductor FETs. In this paper, we simulate the device performance of germanium p-i-n tunneling field effect transistors in the single (SG), double (DG), and nanowire gate-all-around (GAA) geometry. Two key conclusions can be drawn from the results presented here: (1) the ambipolar device characteristics can be completely suppressed by using a source and drain with different doping levels, and (2) the devices realized in the nanowire gate-all-around geometry possess an ON-state current significantly higher than their planar counterparts thanks to their superior electrostatic properties. The simulations were done using Sentaurus Device (copySynopsis), and using Hurkx's model for band-to-band tunneling.