Hardware Implementation of ${\rm GF}(2^{m})$ LDPC Decoders

Low density parity check (LDPC) codes over GF(2
^m
) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2
^m
) codes. This paper proposes a novel variation of the belief propagation algorithm for GF(2
^m
) LDPC codes. The new algorithm results in a reduced hardware complexity when implemented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over GF(2
^m
) are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over GF(2
^m
) decoder is feasible for short to medium length codes. The additional complexity of the decoder is balanced by the superior performance of GF(2
^m
) LDPC codes.