Comprehensive study of 32 nm node ultralow-k/Cu (keff=2.6) dual damascene integration featuring short TAT silylated porous silica (k=2.1)

A comprehensive study of Low-k/Cu integration featuring short TAT (turnaround time) silylated scalable porous silica (Po-SiO, k=2.1) with high porosity (50%) is presented. The TAT for silylation is about 25 % reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, 140 nm pitch dual damascene structure is successfully achieved. The wiring capacitance showed 10 % reduction compared with the conventional porous SiOC (ULK, k=2.65). Sufficient interconnect reliability and packaging characteristics for circuit-under-pad structure are also obtained. The predicted circuit-performance was 8 % higher than ULK in 32 nm node.