Effect of substrate hot carrier stress on high-k gate stack

The origin of stress induced leakage current and defect generation process in the high-k/metal gate stacks under the substrate hot carrier stress and constant voltage stress is investigated. The data suggests that the defects responsible for the SILC increase are located near the high-k/SiO
₂
interface. Generation of these defects is mostly caused by the cold carriers injected from the inversion layer rather than by the hot substrate carriers.