Time-area efficient multiplier-free filter architectures for FPGA implementation

Simultaneous design of multiplier-free filters and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The filter synthesis method is a new approach based on cascade coupling of low order sections. The complexity of the design algorithm is /spl Oscr/ (filter order). The hardware design methodology leads to high performance filters with sampling frequencies in the interval 20-50 MHz. Time-area efficiency and performance of the architectures are considerably above any known approach.