A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13$\ \mu$m CMOS

A 1.25 GS/s 6b ADC is implemented in a 0.13 mum digital CMOS process by time-interleaving two SAR ADCs with 2.5 GHz internal clock frequency that converts 6 bits in 3 cycles. 5.5b ENOB at 1.25 GS/s and 5.8b ENOB at 1 GS/s are achieved without any off-line calibration, error correction or post processing. The entire ADC consumes 32 mW at 1.25 GS/s including T/H and reference buffers, and occupies 0.09 mm
²
.