Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier

In advanced CMOS technologies where device mismatches are of major reliability concern, predicting the input-offset voltage of the sensing circuit is a crucial step in the design process as it has a direct impact on the yield. This work uses the Taylor expansion to derive a criterion to evaluate input-offset voltage of a latch-type voltage-mode sense amplifier. By innovatively setting the correct sensing criterion, this method provides a very simple, yet accurate and robust model to quantify the input-offset of the sense amplifier. The resulting offset expression incorporates three types of device mismatches, namely the threshold voltage (V
_th
), the trans-conductance ( K = ¿C
_0x
W/L) and the capacitance (C). The model is then analyzed under the worst-case scenario. It is shown that V
_th
has the greatest influence on the offset voltage, followed by K and C mismatches. Second-order approximation is also considered when high-level mismatches are present. Extensive simulations have also been carried out to verify the accuracy of the model using three different CMOS technologies.