Power-supply instability aware clock signal modulation for digital integrated circuits

As IC technology scales down, interconnect issues are becoming one of the major concerns of gigahertz System-on-Chip (SoC) design. Voltage distortion (power supply noise) and delay violations (signal and clock skews) dramatically contribute to signal integrity loss. As a consequence, performance degradation, reliability problems and ultimately, functional error occur. In this paper, we propose a new methodology to enhance SoC signal integrity with respect to power/ground voltage transients, without degrading its performance. The underlying principle of the proposed methodology is to dynamically adapt the clock duty-cycle (CDC) according to the signal propagation delay through the logic whose power supply voltage is being disturbed. The methodology is based on a clock stretching logic (CSL) block, which monitors abnormal power grid activity and increases clock duty-cycle accordingly. Moreover, a model to accurately quantify CDC stretching as a function of V
DD
/Gnd fluctuations is proposed. Practical experiments based on the implementation of a 32-bit pipeline processor in a FPGA IC were performed and demonstrate the circuit robustness enhancement to power line fluctuations while maintaining at-speed clock rate.